The invention relates to the field of data communications, and in particular, to facilitating integrated circuit-to-integrated circuit (IC-IC) differential communication involving integrated circuits having different logic topologies, by providing the ability to accept two or more different input/output (I/O) signal voltage levels, which are either direct coupled or AC coupled therewith.
With the increasing needs for communication between IC""s at relatively high data rates, e.g., data rates of above 1.0 Gigabits/second, the use of differential signals is becoming increasingly popular. One reason is because the reduced voltage swings of differential signals increase the achievable maximum data rate. Also, inherent characteristics, such as lower self generated switching noise, reduced electromagnetic interference (EMI), better input noise rejection and power supply rejection, are attractive features of logic having a so-called xe2x80x98differential topologyxe2x80x99.
Particularly in the field of telecommunications, bipolar CML (current mode logic) or PECL (positive emitter-coupled logic) are preferred, due to higher speed, lower skew, and less jitter than a low-voltage differential signal (LVDS), self-timed interface (STI), or dynamic CMOS (complimentary metal oxide semiconductor) design.
However, one problem for the designer is that these differential logic families which are currently popular, are not compatible with each other because of t e different voltage levels used to represent the same logic level!.
By way of explanation, integrated circuitry in the emitter-coupled logic (ECI) family uses bipolar-transistors and has the advantages of being very fast, having high input resistance, having low output resistance, and having low noise generation. However, ECL logic signal levels, referenced to a power supply voltage terminal commonly labeled VCC, are approximately (VCCxe2x88x92VBE) for a logic high voltage, and (VCCxe2x88x922VBE) for a logic low voltage, where VBE is the forward biased base-emitter diode voltage drop of a corresponding bipolar transistor. With ECL, in order to provide the logic high voltage (VCCxe2x88x92VBE), however, an extra transistor is necessary. A similar type of logic using bipolar transistors, known as current-mode logic (CML), eliminates the need for an extra transistor by providing a logic high voltage of VCC, and a logic low voltage of approximately (VCCxe2x88x92VBE). The output level is thus more constrained but in many cases the saving of a transistor is advantageous.
Presently, metal oxide semiconductor (MOS) transistors are commonly fabric ted in integrated circuits along with bipolar transistors. As a result, some logic circuits providing CML level output signals are required to receive at least one input signal compatible with the MOS transistors in addition to receiving at least one CML level input signal.
However, complementary metal oxide semiconductor (CMOS) signal levels differ from ECL. and CML signal levels. In so-called full-swing CMOS signals, a logic high voltage is approximately VCC, whereas a logic low voltage is approximately a second power supply voltage, commonly labeled xe2x80x9cVSSxe2x80x9d, which is negative with respect to VCC. As can be appreciated, when CMOS levels are applied to a base of a bipolar transistor in a CML logic circuit, reliability problems can result because of the differences in logic level voltages.
For example, a large reverse bias, which occurs if a CMOS logic low voltage (about VSS) is applied to the base of an input bipolar transistor while the emitter is held at or near a CML logic high voltage (VCCxe2x88x92VBE), is harmful to the operation of the input bipolar transistor. When a large reverse bias is applied across the base-emitter junction of a bipolar transistor, degradation occurs. Over time, the constant application of this large reverse bias may cause the input bipolar transistor to fail, resulting in a failure of the entire integrated circuit. Electronically, a large reverse bias on a PN junction causes hot carrier injection into the overlying oxide, resulting in poor junction performance. The amount of hot carrier injection is proportional to the time the reverse bias occurs. The size of the reverse bias is related to the mean life of the transistor, for given worst case conditions, by an inverse semi-logarithmic relationship. As the reverse bias decreases linearly, mean life increases exponentially. At typical values for reverse bias, transistor mean life in a mixed CML and CMOS logic circuit may be unacceptably short.
Therefore, full-swing CMOS can damage bipolar circuitry. However, Seven low-voltage differential signal (LVDS) CMOS signals can cause problems with bipolar circuitry, and the low signal levels may not be able to drive the bipolar circuitry.
There may be places in the data communication industry, for example, where a CMOS input/output design is preferred over a bipolar one, e.g., in a computer interface whose CMOS outputs swing rail-to-rail (+VCC to VSS=xe2x88x92VCC), or even in lower-voltage signals where the voltage swings around 1.25 volts by plus and minus 0.50 volts, i.e., between 1.75 and 0.75 volts. Thus, there may be situations where either or both CMOS and bipolar signal levels need to be accommodated.
Because of the present need for both CMOS and bipolar communications, an IC manufacturer currently may have to provide for both CMOS and bipolar communications technologies in different products, or in the same product. Clearly, for the chip manufacturer, it would be advantageous to have a single chip design which accommodates both types of receivers.
A possible solution considered by the inventors would be to provide a design in which one integrated circuit chip has both types of receivers on-board, either of which can be selected during manufacture by metal masking, for example, depending on which technology (CMOS or bipolar) is to be supported in the finished chip. However, a disadvantage of this solution is that the product user would still have to purchase both species of the chip to accommodate a design that uses both technologies. A further disadvantage is the cost of the separate metal mask, and another disadvantage is the time and cost of qualifying two parts.
Another solution considered by the inventors is to have both types of receivers integrated in the finished chip and fully operational with their own separates inputs. However, this solution disadvantageously doubles the differential receiver input pin-out increasing costs.
Therefore, the above-described possible solutions are disadvantageous because of the cost of two chips, the cost of a separate metal mask, and/or the increased pin-out requirement for the package. These disadvantages make these solutions less than optimal.
It would be desirable to be able to accommodate both technologies with one receiver chip without requiring masking or increasing the pin-out.
Therefore, a need exists for an optimal solution to the problem of accommodating both CMOS and bipolar technologies in a single chip (IC) which can receive (and/or send) two different input/output levels, without the disadvantages of the other above-mentioned possible solutions.
U.S. Pat. No. 5,283,482 by Chen, issued Feb. 1, 1994, describes (Abstract) a CMOS circuit for receiving ECL signals which includes a triple-feedback arrangement for dynamically biasing a current source transistor of a differential amplifier of the CMOS circuit. The CMOS receiver circuit has a differential amplifier for generating an output signal representative of the difference between a reference signal and an ECL input signal, and an inverter circuit for receiving the output signal and generating a CMOS compatible output signal. The differential amplifier includes a first current source transistor. A first CMOS transistor is connected to receive the ECL input signal and a second CMOS transistor is connected to receive the reference signal. The first and second CMOS transistors have their drains coupled to first and second load transistors, respectively, and their sources coupled to one another and to a second current source transistor for generating a first control signal representative of the difference between the ECL input signal and the reference signal at the drain. of the first CMOS transistor. A first feedback path connects the first control signal to the second current source transistor. A second feedback path connects the first control signal to the first and second load transistors. A third feedback path connects the drain of the second CMOS transistor to the first current source transistor for dynamically biasing the first current source transistor.
However, this only provides for receiving ECL signals (bipolar) and converting them to CMOS signals for use in CMOS circuitry. The circuitry is not for receiving two different types of differential inputs. Further, the circuitry provides a differential input to single ended, full swing output conversion, as opposed to being a fully differential circuit.
U.S. Pat. No. 5,113,095 by Huehne, issued May 12, 1992, describes (Abstract) a logic circuit for receiving both CMOS and CML level input voltages which performs a logical OR function. A reference bipolar transistor is coupled to a first power supply voltage terminal through a first resistor. A second bipolar transistor for receiving a CML level input signal is coupled to the first power supply voltage terminal through a second resistor. Emitters of the bipolar transistors are connected together. A MOS transistor for receiving a CMOS level input signal has a drain connected to a collector of the second bipolar transistor, and a voltage dropping portion separate the source of the MOS transistor from the emitters of the reference transistor and the bipolar transistor. The input voltages control a constant current conducted from a current source connected to the source of the MOS transistor. The logic circuit allows mixed logic levels without subjecting the bipolar transistors to a large base-to emitter reverse bias caused by CMOS logic levels.
However, this prior known arrangement is an OR gate with two inputs, where one input is CMOS level and the other is single-ended CML. Therefore, the arrangement is not a receiver per se, is not for differential signals, and would not work for high-speed communications.
U.S. Pat. No. 4,958,133 Bazes issued Sep. 18, 1990 describes (Abstract) a CMOS complementary, self-biased, differential amplifier which provides for a rail-to-rail common-mode input-voltage range of operation. A self-biasing scheme is used to provide negative feedback to the amplifier in order to assist in providing a common-mode rejection but providing high gain amplification for differential-mode amplification. With reference to the patent FIG. 1, essentially, this amplifier receives differential inputs (A-11 and B-12) and produces a single-ended output (OUT-13). An apparently related IEEE Journal of Solid-State Circuits, Vol. 26, No. 2, February 1991, by Mel Bazes, describes xe2x80x9cTwo Novel Fully Complementary Self-Biased CMOS Differential Amplifiersxe2x80x9d (Title).
IBM Technical Disclosure Bulletin Vol. 34, No. 3, August 1991 (pages 254-255) describes a xe2x80x9cHigh-Speed Bipolar Voltage/Current Receiver Circuitxe2x80x9d (Title) for a serial link with the receiver requiring 2 differential inputs, 4 pins, per channel. The circuit described provides a means of inputting either emitter coupled logic (ECL) or current mode logic (CML,) signals in a single integrated circuit. However, this arrangement requires separate input pins for the respective signals. Therefore, it would not be practical for a parallel link due to the receiver requiring two differential inputs (4 pins) per channel. For a single channel, the arrangement is fine. However, for 12 channels, for example, the pin requirement disadvantageously jumps to 48. Packaging is a premium, and contributes to cost.
Therefore, a need exists for a selectable receiver for accommodating both bipolar and CMOS type signals without the disadvantages of the prior solutions.
There is known an IEEE Standard for Low-Voltage Differential Signals (LVDS) for Scaleable Coherent Interface (SCI) (IEEE Std 1596.3-1996). A Scaleable Coherent Interface (SCI), specified in IEEE Std 1596-1992, provides computer-bus-like services but uses a collection of fast point-to-point links instead of a physical bus in order to reach far higher speeds. The base specification defines differential ECL signals, which provide a high transfer rate (16 bits are transferred every 2 ns), but are inconvenient for some applications. Therefore, IEEE Std 1596.3-1996, an extension to IEEE Std 1596-1992, defines a lower-voltage differential signal (as low as 250 mV swing) that is compatible with low-voltage CMOS, BiCMOS, and GaAs circuitry. The power dissipation of the transceivers is low, since only 2.5 mA is needed to generate this differential voltage across a 100-ohm termination resistance. Signal encoding is defined that allows transfer of SCI packets over data paths that are 4-, 8-, 32-, 64-, and 128-bits wide. Narrow data paths (4 to 8 bits) transferring data every 2 ns can provide sufficient bandwidth for many applications while reducing the physical size and cost of the interface. The wider paths may be needed for very-high-performance systems.
There is a known low-voltage differential signal (LVDS) CMOS interface called the self timed interface (STI). Briefly, a self-timed interface (STI) provides a clock signal which clocks bit serial data onto a parallel, electrically conductive bus and the clock signal is transmitted on a separate line of the bus. The received data on each line of the bus is individually phase aligned with the clock signal. The received clock signal is used to define boundary edges of a data bit cell individually for each line and the data on each line of the bus is individually phase adjusted so that, for example, a clock transition position is in the center of the data cell. See for example U.S. Pat. No. 5,832,047, Ferraiolo et al., dated Nov. 3, 1998, entitled xe2x80x9cSELF TIMED INTERFACExe2x80x9d assigned to the same assignee as the present application.
However, a need exists for a receiver with the flexibility of AC or DC coupling. In particular, a selectable low-voltage differential signal/current mode logic (LVDS/CML) receiver which supports both AC and DC coupling.
A large amount of equipment is already in the field for data communications, telecommunications, and the computer industry, and all have slightly different input/output level requirements. However, they all share the need for higher speed communication, with smaller packages, and lower cost.
Therefore, a need also exists for an improved relatively high-speed receiver which can accommodate the various technologies, e.g., a 3.3 VDC (LVDS) selectable STI/CML receiver with respective bandwidths of DC up to 1.6/2.2 Gigabit/s, which would enable an IC manufacturer to serve two large established communications customer bases, while only developing, testing, and supporting one chip.
It is, therefore, a principle object of this invention to provide a method an d apparatus for a selectable relatively high-speed differential receiver, in particular, a selectable receiver with the option of AC or DC coupling.
It is another object of the invention to provide a method and apparatus that solves the above mentioned problems so that a selectable receiver with the option of AC or DC coupling is provided while pin numbers are kept to a minimum.
These and other objects of the present invention are accomplished by the method and apparatus disclosed herein.
A 3.3-volt selectable low-voltage differential/current mode logic, e.g., STI/CML, receiver according to an exemplary embodiment of the invention, solves the problems discussed at the outset, in addition to offering the choice of AC or DC coupling, with bandwidth suitable for DC to greater than Gigabit per second data transmission speed.
Advantageously, the novel receiver can achieve requirements of two customers with the same data communication needs, but different input/output level requirements.
According to an aspect of the invention, an exemplary receiver is a fully differential high speed receiver.
According to an aspect of the present invention, the exemplary interface is fully differential, receives two types of differential signals, and provides AC or DC coupling. By contrast, U.S. Pat. No. 5,283,482, for example, describes differential to single ended conversion, full swing output.
According to an aspect of the present invention, pin requirements are kept to a minimum. For 12 channels, for example, only 24 pins would be required in the exemplary embodiment. As mentioned in the Background section above, a prior arrangement for a serial link, described in the IBM TDB (Vol. 34, No. 3, 1991), is not practical for a parallel link due to the receiver requiring two differential inputs 4 pins per channel. For 12 channels, for example, the pin requirement jumps to 48. Since packaging is a premium, and contributes to cost, the present invention has advantages in this regard.
These and other aspects of the invention will become apparent from the detailed description set forth below.